AEAT-84AD 14/12 bit multi-turn encoder module data sheet description the AEAT-84AD provides all functions as an optoelec- tronic-mechanical unit in order to implement, with single turn absolute encoder, an absolute multiturn encoder with a combined capacity of up to 30 bits at extended temperature. the unit consists of an ir-led circuit board, a phototrans- istor (pt) circuit board, and 6 or 7 gear wheels arranged in between the pcbs. specifi cations the multi-turn unit is available in the following versions: ? 12-bit solid shaft ? 14-bit solid shaft features ? 16384 (14bits) and 4096 (12bits) revolution count versions ? optical, absolute multi-turn assembly with max. ? 55 mm and typical height 12.2 mm. ? operating temperatures of -40 c to +125 c ? mechanical coupling by means of 14 teeth gear pinion with module of 0.3 ? operating speeds up to 12,000 rpm ? a 2 x 4-pole pin strip for power supply and signal applications ? major component of multi-turn housed encoder ? cost eff ective solution for direct integration into oem systems ? linear positioning system benefi ts ? no battery or capacitor required for number of revolu- tion counting during power failure ? immediate position detection on power up
2 package dimensions figure 2. block diagram figure 1. package dimensions notes: 1. 3rd angle projection 2. dimensions are in millimeters 3. example of matching connector: mpe garry 521 series, no. bl21-43ggg-008 block diagram and detailed description in the following descriptions, the i/o pins are enclosed by a box, e.g., mtmux[2:0]. 3 7x 3 pt's comparator 1 of 8-decoder 3 x 4k7 3 3 7x 3 ir's 3 3 x 100k mtmux[2:0] mtdat[2:0] vcc (+5v) gnd 3 x 4k7
3 multiplexing and position data each of the 1:4 reduced 7 coded gear wheels generates a 3-bit code, from which the 14-bit gray code can be generated as position data through v-bit processing. the 3-bit code is identical electrically for all gear wheels, only the projection on the mechanical angle (the revolu- tions) is diff erent according to the 1:4 divisions. the code and the data bits and vbits to be generated are shown in the figure 3 for the gear wheel 1: the 3-bit codes of the gear wheels 1 to 7 are output on mtdat[2:0] demultiplexed with mtmux[2:0] . here, the binary value on mtmux[2:0] corresponds to the gear- wheel number (1 = gear wheel 1, 2 = gear wheel 2, etc.). the confi guration is displayed with the value 0. table 1 shows the assignments: 1 msb singleturn 0 2 3 4 shaft turns 1. mtdat[0] 1. mtdat[1] 1. mtdat[2] 1. wheel turns 1 0 gray code (generated) data-bit1 data-bit2 v-bit2 figure 3. multiplexing diagram for gear wheel 1 table 1. demultiplexing diagram for all gear wheels bin/dec mtmux[2:0] mtdat[2] mtdat[1] mtdat[0] notes 001 / 1 010 / 2 to 111 / 7 3-bit gear wheel 1 3-bit gear wheel 2 to 3-bit gear wheel 7 000 / 0 always 1 0 = 12 bit 1 = 14 bit 1 = solid shaft 1 note: 1. applicable for aeax-84ad solid shaft version only
4 gray code-generation for the readout schematic of the multi-turn code gears, i.e. with the users microcontroller, there must be a logical replication of the v-bit multiplexers. this can be done by a bit manipulation or by look up tables. care needs to be taken with the real time readout conditions. the procedure is as follows : 1. the 3 bits ( mtdat[2:0] ) of each gear (c1[2:0] to c7[2:0]) are continuously de-multiplexed. thus there are maximal 3 bits x 7gears = 21-bit AEAT-84AD data in parallel. 2. synchronous to the readout of the single turn absolute encoder, those AEAT-84AD bits (depending on the msb bit, i.e. sel-bit, of the single turn encoder) needs to be complemented to the complete gray code word (cascading). 3. the bit change of the complete gray code will be synchronized by the single turn absolute encoder and thus electronically eliminating gear play. the logic diagram for one gear is shown in the following diagram (vbit- multiplexer), figure 4. logic diagram from mtdat-demux (code-wheel x) sel cx[0] cx[2] cx[1] d1 1 s y 0 s 1 xor s 1 y 0 d2 y 1 s 0 0 y 4x mux2 v2 (v-bit2) (data-bit2) (data-bit1) figure 4. logic diagram and truth table for one of the gear wheels sel cx[0] cx[1] cx[2] d1 d2 v2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
5 v-bit-multiplexer cascade gray-bit1 gray-bit0 c1[0] gray-bit14 gray-bit12 d1 sample aeas-7000 msb demuxed code-wheel 1 sel cx[0] cx[1] cx[2] d2 v2 c1[1] c1[2] c2[0] c2[2] c2[1] cx[0] sel cx[2] cx[1] d1 v2 d2 gray-bit2 gray-bit3 c5[1] c5[0] cx[1] sel cx[0] c5[2] cx[2] gray-bit9 d2 d1 gray-bit8 v2 c6[1] c6[0] cx[1] sel cx[0] c6[2] cx[2] gray-bit11 (msb for 12bit) d2 d1 gray-bit10 v2 c7[1] c7[0] cx[1] sel cx[0] c7[2] cx[2] gray-bit13 (msb for 14bit) d2 d1 gray-bit12 v2 demuxed code-wheel 2 demuxed code-wheel 5 demuxed code-wheel 6 demuxed code-wheel 7 figure 5. the cascading of v-bit-multiplexer of all gear wheels the figure 5 shows the cascading of the v-bit- multiplexer of all gear wheels. the outputs are the 14bits gray code in parallel. the msb of the complete code is dependant on the total resolution of the system. it can be used in steps of 2 bits (14bit,12bit,etc). unused higher bits should be masked to logical zero. with the data-multiplexer ic version of the multi-turn encoder module, the data multiplexer ic will perform the complete driving and data processing of the encoder units while maintaining all time constraints. there is an ic available to combine both the aeas-7x00 13/16 bit single turn component and the aeax- 84ad 12/14 bit multiturn module into one-single powerful multi-turn absolute encoder. this one-stop solution enables the design of a high-end absolute encoder with minimum component count at integration level. figure 6 shows an application example of integration of single- turn absolute encoder and multiturn module using muic. note: to simplify the synchronization with single-turn absolute encoder (e.g. aeas-7000), the total solution has been embedded into a single chip C muic. please refer to the ordering information for this device.
6 figure 6. application example of integration of single-turn absolute encoder module and multiturn module using muic. application example of multiturn absolute encoder device selection guide 1 part number resolution operating temperature (c) output format dc supply voltage (v) AEAT-84AD-lbsc0 12 bit -40 to 125 multiplexed 5.0 to 5.5 AEAT-84AD-lbsf0 14 bit -40 to 125 multiplexed 5.0 to 5.5 note: 1. ssi interface is enabled through muic. please refer to ordering information for muic.
7 absolute maximum ratings 1, 2 parameter symbol limits units dc supply voltage v cc -0.3 to +6.0 v input voltage v i -0.5 to 5.5 v output voltage v o -0.5 to +v cc +0.5 v moisture level (non-condensing) %rh 85 % encoder shaft speed s rpm max 12000 rpm storage temperature t stg -40 to 125 c notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this s pecifi cation is not implied. 2. exposure to absolute maximum rating conditions for extended periods may aff ect reliability. 3. this device meets the esd ratings of the iec61000-4-2 level 2 (4 kv). recommended operating conditions description symbol values units notes dc supply voltage v cc -0.5/+5.5 v ambient temperature t amb -40 to +125 c multiplex read delay t dmuxrd 64 ? s encoder shaft speed s rpm 10000 or below rpm 1 note: 1. as unique coded gear-wheels techniques are implemented to generate unambigous positional information, the interactions betwe en these highly wear-resistant gear wheels are subjected to mechanical wear and tear. dc characteristics dc characteristics over recommended operating range, typical at 25c parameter symbol condition values units min typ. max mtdat[2:0] output high voltage (10 k pull-up) v oh i oh = -50 ? a 4.0 v mtdat[2:0] output low voltage (4k7 series-r) v ol i ol = -50 ? a 0.4 v input high voltage v ih v cc = 5.0 v v cc = 5.5 v 3.2 3.9 v input low voltage v il 0.8 v mtmux[2:0] input current, vin-vcc or 0 v i il /i ih 100 k pull-down -10 100 ? a vcc supply current i cc 68 76 ma
8 timing characteristics timing characteristics over recommended operating range, typical at 25 c parameter symbol condition values units min typ. max input transition rise/fall time t r /t f 0.8/3.0 v 500 ns multiplex read delay t dmuxrd 64 ? s encoder shaft speed s rpm max 12000 12000 rpm figure 7. timing characteristics of mtmux[2:0] and mtdat[2:0] mtdat[2:0] mtmux[2:0] t dmuxrd old value old value new value new value see detail 1 detail 1 1 3 5 7 2 4 6 8 figure 8. pin confi guration electrical connections pin description 1 gnd 2 mtdat2 3 mtdat1 4 mtdat0 5 mtmux2 6 mtmux1 7 mtmux0 8vcc
9 zero position of coupling wheel plastic plug pinion, module 0.3, 14 teeth plastic plug is removed upon integration with gearwheel. application note the encoder is mechanically fi xed by means of holes in adapters, which accommodate m3 threads. the encoder has 2 adapters for attaching in a 3 x 120 and 4 x 90 arrangement. for details, please refer to the mechanical drawings in figure 1. the mechanical coupling of the encoder shaft is realised by means of gear pinion with a module of 0.3, 14 teeth. the zero positions of the coupling wheels are locked with a plastic plug for alignment to the single turn absolute encoder, with the coupling wheel being able to compen- sate for an angle error of about +/-7. the electrical connection is realized by means of a 2 x 4 pin strip (1.27mm pitch), which is plugged into a corre- sponding female connector. the encoder is attached with a plastic plug that locks the absolute zero position. during the mating of the gear pinion and the encoder coupling gear wheel it may be necessary to align the teeth of the gears for proper matching. the plastic plug can be removed upon integra- tion with the gear wheel. figure 9. mechanical coupling with multiturn encoder module
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2012 avago technologies. all rights reserved. obsoletes av01-0275en av02-3573en - june 11, 2012 ordering information AEAT-84AD-lbsc0 multi-turn, -40 to +125 c, solid shaft, serial, 12 bit AEAT-84AD-lbsf0 multi-turn, -40 to +125 c, solid shaft, serial, 14 bit for ordering information of muic, please refer to factory.
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